June 26-30, 2023 Prague, Czech Republic + Virtual View More Details & Registration Note: The schedule is subject to change.
The Sched app allows you to build your schedule but is not a substitute for your event registration. You must be registered for Embedded Open Source Summit 2023 to participate in the sessions. If you have not registered but would like to join us, please go to the event registration page to purchase a registration.
This schedule is automatically displayed in Central European Summer Time (UTC/GMT +2). To see the schedule in your preferred timezone, please select from the drop-down menu to the right, above "Filter by Date."
IMPORTANT NOTE: Timing of sessions and room locations are subject to change.
Embedded systems often come with LCD panel for visualization. Making such system available in a board farm for remote access and CI testing is a challenging task often full of compromises. Testing each software update and verifying whether a panel is still running within precise panel vendor timing specification is even harder. This led to an idea to build a device, where the content sent to the panel is captured using an FPGA and passed to a PC for analysis, including pixel-by-pixel auxiliary signal state details. First part of the talk documents the journey toward this device, which became an FPGA video and signal capture PHY and USB UVC bridge, including development issues and failed attempts. The second part of the talk explains the design, the content of the FPGA, the USB FIFO controller, and the challenges of building PCB for such a high-frequency setup in hobby project conditions. Marek built this hardware at home, and so can you. Finally, a demo shows how this tool is used to measure the precise timing of PWM and synchronization signals of the panel to verify it is running within specification from panel vendor, and the image on display is exactly as it should be.
